Clock gating
TECHNIQUE USED IN SYNCHRONOUS CIRCUITS FOR REDUCING DYNAMIC POWER DISSIPATION, BY ADDING MORE LOGIC TO A CIRCUIT TO PRUNE THE CLOCK TREE (DISABLING PORTIONS OF THE CIRCUITRY SO THAT THE FLIP-FLOPS IN THEM DO NOT HAVE TO SWITCH STATES)
Perfect clock gating; Clock gate; Integrated clock gating; Dynamic clock gating; Autonomous peripheral clock gating; Autonomous state-based clock gating; Autonomous hardware clock gating; Autonomous clock gating; Fine grain clock gating; Sequential clock gating; Clock gating logic; Gated clock; Clock-gated
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use. Clock gating saves power by pruning the clock tree, at the cost of adding more logic to a circuit.